Power MOS devices, including laterally diffused metal-oxide-semiconductor (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. A conventional LDMOS device utilizes a multiple-level metal fabrication process for forming an interconnection between regions of differing conductivity types (e.g., n-type and p-type) in a source region of the device. The source current is then generally routed via a low resistance p-type region to the back of the wafer, where a source contact is formed.
In applications where high-frequency operation is desired, such as in a radio frequency (RF) range (e.g., above 1 gigahertz (GHz)), the conventional methodology for forming the LDMOS device results in a relatively high input capacitance Cgs (e.g., about 80 picofarad (pF) for a 50 micron device). The high input capacitance can cause a variety of undesirable effects, including device mismatching, narrow bandwidth, and low power gain. In order to minimize the input capacitance in the LDMOS device, a conventional approach has been to scale back the source contact area, thereby increasing a distance between the gate and the source interconnection of the device. While this approach may reduce the input capacitance of the LDMOS device, a source resistance Rs of the device is substantially increased due, at least in part, to the reduction in source contact area. In some cases, the increase in source resistance significantly undermines any beneficial reduction in the input capacitance provided by scaling back the source contact area.
Previous attempts to improve the high-frequency performance of the LDMOS device have primarily focused on optimizing the trade-off between input capacitance and source resistance. These prior attempts, however, have been unsuccessful at providing a CMOS process compatible LDMOS device capable of high-frequency operation. Accordingly, there exists a need for an LDMOS device capable of improved high-frequency performance which does not suffer from one or more of the above-noted deficiencies of the prior art. Furthermore, it would be desirable if such an LDMOS device was fully compatible with a CMOS process technology.